GPIO pin configuration
From ShadoWiki
When the PXA27x is reset the GPIO pin direction registers (GPDRx) are cleared and all GPIO pins are configured as inputs. For GPIO pins that get configured as outputs, control is achieved by writing a one to the corresponding GPIO Pin-Output Set register or the GPIO Pin-Output Clear register (which are write only registers GPSRx/GPCRx) for that pin. Until a pin is configured as an output writing to these registers has no effect. When a given pin gets configured as an output (and the PH Peripheral Hold register is not set) the most recent write to the corresponding set or clear register sets the output state of that pin.
The GPIO alternate function registers (GAFRx_L/GAFRx_U) have 2 bit settings per pin. A zero setting makes the pin a generic GPIO pin. To select an alternate GPIO pin function a bit setting of 0b01, 0b10 or 0b11 sets alternate function 1, 2 or 3 respectively.
This subroutine sets the GPIO pin-output state control registers, the GPIO pin direction control registers (output enable) and the GPIO alternate function control registers. It also sets up the Pulse Width Modulator control register 2 (PWM<2>) for a 50% duty cycle output.
ROM:0000018A
ROM:0000018A sub_18A
ROM:0000018A LDR R1, =dword_664 ; R1=0x0664 @ 0x03B4
ROM:0000018C PUSH {R4,R5,LR} ; R4=0x0800_0024, R5=0, LR=0x033E
ROM:0000018E ADD R2, R0, #0 ; R2=0, R0=0 R0 = scratch pad status
ROM:00000190 SUB R1, #0x7C ; R1=0x05E8
ROM:00000192 LDR R3, [R1,#0x44] ; R3=0x60CC_0000 @ 0x062C
ROM:00000194 CMP R2, #0 ; R2=0 check scratch pad status
ROM:00000196 LDR R0, =0x40E00000 ; GPIO controller base addr.
ROM:00000198 LDR R4, =0x40F00000 ; Power Mgr & Reset Cntrlr base addr.
ROM:0000019A BNE loc_1FC ; exit sub if Scratch Pad Reg != 0
ROM:0000019A ; (PSPR PwrMgrScratchPadReg)
ROM:0000019C LDR R2, [R1,#0x3C] ; R2=0x0218_0C00
ROM:0000019E STR R2, [R0,#0x18] ; set GPSR0(GPIO PinOutputSet)<31:0>
ROM:0000019E ; set:PS10, PS11, PS19, PS20 & PS25
ROM:0000019E ; (set pin state High)
ROM:000001A0 LDR R2, [R1,#0x38] ; R2=0x0000_0000
ROM:000001A2 STR R2, [R0,#0x1C] ; set GPSR1(GPIO PinOutputSet)<63:32>
ROM:000001A2 ; set:None of 32:63
ROM:000001A4 LDR R2, [R1,#0x34] ; R2=0x0080_C000
ROM:000001A6 STR R2, [R0,#0x20] ; set GPSR2(GPIO PinOutputSet)<95:64>
ROM:000001A6 ; set:PS78, PS79 & PS87
ROM:000001A8 LDR R2, =0x40E00100 ; (adjust base addr)
ROM:000001AA LDR R5, [R1,#0x30] ; R5=0x0110_0000
ROM:000001AC STR R5, [R2,#0x18] ; set GPSR3(GPIOPinOutputSet)<120:96>
ROM:000001AC ; set:PS116 & PS120
ROM:000001AC ;
ROM:000001AE LDR R5, [R1,#0x4C] ; R5=0x0FA8_4000
ROM:000001B0 STR R5, [R0,#0x24] ; set GPCR0(GPIOpinOutputClr)<31:0>
ROM:000001B0 ; set:PC14,PC19,PC21 & PC23-PC27
ROM:000001B0 ; (set pin state Low)
ROM:000001B2 LDR R5, [R1,#0x48] ; R5=0x0300_3F8C
ROM:000001B4 STR R5, [R0,#0x28] ; set GPCR1(GPIOpinOutputClr)<63:32>
ROM:000001B4 ; set:PC34,PC35,PC39-PC45,PC56,PC57
ROM:000001B4 ; R3=0x60CC_0000
ROM:000001B6 STR R3, [R0,#0x2C] ; set GPCR2(GPIOpinOutputClr)<95:64>
ROM:000001B6 ; set:PC82,PC83,PC86,PC87,PC93,PC94
ROM:000001B8 LDR R3, [R1,#0x40] ; R3=0x0084_0000
ROM:000001BA STR R3, [R2,#0x24] ; set GPCR3(GPIOpinOutputClr)<120:96>
ROM:000001BA ; set:PC114 & PC119
ROM:000001BA ;
ROM:000001BC LDR R3, [R1,#0x2C] ; R3=0xCFB9_0C00
ROM:000001BE STR R3, [R0,#0xC] ; set GPDR0(GPIOpinDirReg)<31:0>
ROM:000001BE ; set:PD10,PD11,PD16,PD19-PD21,
ROM:000001BE ; PD23-27,PD30 & PD31
ROM:000001BE ; (set as Output)
ROM:000001C0 LDR R3, [R1,#0x28] ; R3=0xFF22_BF8F
ROM:000001C2 STR R3, [R0,#0x10] ; set GPDR1(GPIOpinDirReg)<63:32>
ROM:000001C2 ; set:PD32-PD35,PD39-PD45,PD47,PD49
ROM:000001C2 ; PD53 & PD56-PD63
ROM:000001C4 LDR R3, [R1,#0x24] ; R3=0xF2CD_FFFF
ROM:000001C6 STR R3, [R0,#0x14] ; set GPDR2(GPIOpinDirReg)<95:64>
ROM:000001C6 ; set All EXCEPT: PD81,PD84 & PD85,
ROM:000001C6 ; PD88,PD90 & PD91
ROM:000001C8 LDR R0, [R1,#0x20] ; R0=0x01F5_FF81
ROM:000001CA STR R0, [R2,#0xC] ; set GPDR3(GPIOpinDirReg)<120:96>
ROM:000001CA ; set:PD96,PD103-PD112,PD114 &
ROM:000001CA ; PD116-PD120
ROM:000001CA ;
ROM:000001CC LDR R0, =0x40E00000 ; (restore GPIO Controller base addr)
ROM:000001CE LDR R2, [R1,#0x1C] ; R2=0x0E80_0000
ROM:000001D0 ADD R0, #0x40 ; R0=0x40E0_0040 (offset base addr)
ROM:000001D0 ;
ROM:000001D2 STR R2, [R0,#0x14] ; set GAFR0_L(GPIOaltFuncLow)<15:0>
ROM:000001D2 ; set:AF11=2,AF12=2,AF13=3
ROM:000001D4 LDR R2, [R1,#0x18] ; R2=0xA500_001A
ROM:000001D6 STR R2, [R0,#0x18] ; set GAFR0_U(GPIOaltFuncUp)<31:16>
ROM:000001D6 ; set:AF16=2,AF17=2,AF18=1,
ROM:000001D6 ; AF28=1,AF29=1,AF30=2 & AF31=2
ROM:000001D8 LDR R2, [R1,#0x14] ; R2=0x6000_000A
ROM:000001DA STR R2, [R0,#0x1C] ; set GAFR1_L(GPIOaltFuncLow)<47:32>
ROM:000001DA ; set:AF32=2,AF33=2,AF46=2 & AF47=1
ROM:000001DC LDR R2, [R1,#0x10] ; R2=0xAAA0_3959
ROM:000001DE STR R2, [R0,#0x20] ; set GAFR1_U(GPIOaltFuncUp)<63:48>
ROM:000001DE ; set:AF48=1,AF49=2,AF50=1,AF51=1,
ROM:000001DE ; AF52=1,AF53=2,AF54=3,AF58-63=2
ROM:000001E0 LDR R2, [R1,#0xC] ; R2=0x22AA_AAAA
ROM:000001E2 STR R2, [R0,#0x24] ; set GAFR2_L(GPIOaltFuncLow)<79:64>
ROM:000001E2 ; set:AF64-AF76=2 & AF78=2
ROM:000001E4 LDR R2, [R1,#8] ; R2=0x4144_0F0A
ROM:000001E6 STR R2, [R0,#0x28] ; set GAFR2_U(GPIOaltFuncUp)<95:80>
ROM:000001E6 ; set:AF80=2,AF81=2,AF84=3,AF85=3,
ROM:000001E6 ; AF89=1,AF91=1,AF92=1,AF95=1.
ROM:000001E8 LDR R2, [R1,#4] ; R2=0x56AA_95FF
ROM:000001EA STR R2, [R0,#0x2C] ; set GAFR3_L(GPIOaltFuncLow)<111:96>
ROM:000001EA ; set:AF96-AF99=3,AF100-AF102=1,
ROM:000001EA ; AF103-AF108=2,AF109-AF111=1
ROM:000001EC LDR R1, [R1] ; R1=0x0000_1401
ROM:000001EE STR R1, [R0,#0x30] ; set GAFR3_U(GPIOaltFuncUp)<120:112>
ROM:000001EE ; set:AF112=1,AF117=1 & AF118=1
ROM:000001EE ;
ROM:000001F0 MOV R0, #0x30 ; R0=0x30
ROM:000001F2 STR R0, [R4,#4] ; set PSSR (PwrMgrSleepStatusReg)
ROM:000001F2 ; set:PH=1 (PeripheralCntrlHold=ON)
ROM:000001F2 ; (HoldPinsInSleepModeState)
ROM:000001F2 ; RDH=1 (ReadDisableHold=ON)
ROM:000001F2 ; (DisableGPIOrecievers)
ROM:000001F2 ;
ROM:000001F4 LDR R1, =0x40B00000 ; R1=0x40B0_0000 PWM contrl Registers
ROM:000001F6 MOV R0, #1 ; R0=1
ROM:000001F8 STR R0, [R1,#0x14] ; PWMDCR2 (PulsWidthModDutyCycReg)
ROM:000001FA STR R0, [R1,#0x18] ; PWMPCR2 (PulsWidthModPeriodReg)
ROM:000001FA ; set: PWM<2> for 50% Duty cycle
ROM:000001FC loc_1FC ;
ROM:000001FC POP {R4,R5,PC} ; ret
ROM:000001FC
ROM:000001FC ; End of function sub_18A
